FPAG DDR2 SDRAM程序分析

2022-02-13

FPGA

字数统计: 1.5k | 阅读时长≈ 8 分钟

一、ddr_test.v

状态机切换：

state=IDLE , next_state=MEM_WRITE

wr_burst_addr=25'd0;
wr_burst_req <= 1'b1;      //产生ddr burst写请求       
wr_burst_len <= 10'd255;
wr_cnt <= 10'd0;

/*burst读长度*/	
always@(posedge	mem_clk)
	begin
		if(state == IDLE && rd_burst_req)
			length <= rd_burst_len;
		else
			length <= length; 
	end

mem_burst_v2.v

state=IDLE , next_state=MEM_WRITE_FIRST / MEM_WRITE_BURST_BEGIN

/*local写请求信号*/
assign local_write_req = ((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_WRITE));

if(wr_burst_req && wr_burst_len != 10'd0)    /*接收到burst写请求*/
    next_state <= MEM_WRITE_FIRST;    /*状态转为第一次写*/

state=MEM_WRITE ,next_state=MEM_WRITE

wr_burst_addr=wr_burst_addr;
if(wr_burst_data_req)       //写入burst数据请求 
    begin
        wr_burst_req <= 1'b0;
        wr_burst_len <= 10'd255;
        wr_cnt <= wr_cnt + 10'd1;  //测试数据(每字节)加1
    end

mem_burst_v2.v

/*写入数据请求信号*/
wr_burst_data_req = (state == MEM_WRITE_FIRST ) || (((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_WRITE)) && local_ready && ~last_wr_burst_data_req);

state= MEM_WRITE, next_state= MEM_READ (wr_burst_finish=1)

wr_burst_addr=wr_burst_addr;

state= MEM_READ, next_state= MEM_READ

wr_burst_addr=wr_burst_addr;
if(rd_burst_data_valid)     //检测到data_valid信号,burst读请求变0 rd_burst_data_valid = local_rdata_valid
    begin
        rd_burst_req <= 1'b0;
        rd_burst_len <= 10'd255;
        rd_cnt <= rd_cnt + 10'd1;
    end

state=MEM_READ, next_state= MEM_WRITE (rd_burst_finish=1)

wr_burst_addr <= wr_burst_addr + {{(ADDR_WIDTH-8){1'b0}},8'd255}; //地址加burst长度255   

wr_burst_req <= 1'b1;      //产生ddr burst写请求       
wr_burst_len <= 10'd255;
wr_cnt <= 10'd0;

二、mem_burst_v2.v

assign local_burstbegin = ((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_READ)); /*产生local burst begin信号*/

state=IDLE , next_state=MEM_WRITE_FIRST

(wr_burst_req && wr_burst_len != 10'd0) == 1; /*接收到burst写请求*/
if(wr_burst_req)
    wr_remain_len <= wr_burst_len;  /*wr_remain_len赋初值*/
else
    wr_remain_len <= wr_remain_len;

if(state == IDLE && rd_burst_req)
    local_size <= (rd_burst_len >= burst_size) ?  burst_size : rd_burst_len ;
else if(state == IDLE && wr_burst_req)
    local_size <= (wr_burst_len >= burst_size) ?  burst_size : wr_burst_len;


if(rd_burst_req)     /*读burst请求有效*/
    begin
        local_address <= rd_burst_addr;
        rd_addr_cnt <= 10'd0;
    end
else if(wr_burst_req) /*读burst请求有效*/
    begin
        local_address <= wr_burst_addr;
        rd_addr_cnt <= 10'd0;
    end
else
    begin
        local_address <= local_address;
        rd_addr_cnt <= 10'd0;
    end

state=MEM_WRITE_FIRST , next_state=MEM_WRITE_BURST_BEGIN

if(next_state == MEM_WRITE_BURST_BEGIN)
    burst_remain <= burst_size;        /*burst size is 2*/

state=MEM_WRITE_BURST_BEGIN , next_state= MEM_WRITE_BURST_BEGIN

(burst_remain == 1 && local_ready) == 1;/*一次local burst写完成, 重新回到burst begin */
/*计算最后一个burst数据写请求信号*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_WRITE_BURST_BEGIN || state == MEM_WRITE)
			if(wr_remain_len == 10'd2 && local_ready)
				last_wr_burst_data_req <= 1'b1;
			else
				last_wr_burst_data_req <= last_wr_burst_data_req;
		else
			last_wr_burst_data_req <= 1'b0;
	end

if(local_ready)
    wr_remain_len <= wr_remain_len - 10'd1;
else
    wr_remain_len <= wr_remain_len;

if(next_state == MEM_WRITE_BURST_BEGIN)
    burst_remain <= burst_size;        /*burst size is 2*/

if( ((state == MEM_WRITE_BURST_BEGIN) || (state == MEM_WRITE)) && local_ready)      /*一次数据写入有效*/
    burst_remain <= burst_remain - 1;

if(state == MEM_WRITE_BURST_BEGIN && (next_state == MEM_WRITE_BURST_BEGIN) && local_ready)
    if((wr_remain_len - 1) > burst_size)  /*判断剩余写数据长度是否大于burst_size*/
        local_size <= burst_size;
else
    local_size <= wr_remain_len - 1;

if(local_ready && (next_state == MEM_WRITE_BURST_BEGIN))
    begin
        local_address <= local_address + {14'd0,burst_size};  /*Bust begin写,地址加burst_size*/
    end                                                       /*即MEM_WRITE_BURST_BEGIN写两个数据*/
else
    begin
        local_address <= local_address;
    end

assign local_burstbegin = ((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_READ)); /*产生local burst begin信号*/

state=MEM_WRITE_BURST_BEGIN , next_state= MEM_WRITE

local_ready==1; /*burst begin完成, 转到数据写入*/
/*计算最后一个burst数据写请求信号*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_WRITE_BURST_BEGIN || state == MEM_WRITE)
			if(wr_remain_len == 10'd2 && local_ready)
				last_wr_burst_data_req <= 1'b1;
			else
				last_wr_burst_data_req <= last_wr_burst_data_req;
		else
			last_wr_burst_data_req <= 1'b0;
	end


if(local_ready)
    wr_remain_len <= wr_remain_len - 10'd1;
else
    wr_remain_len <= wr_remain_len;

if( ((state == MEM_WRITE_BURST_BEGIN) || (state == MEM_WRITE)) && local_ready)      /*一次数据写入有效*/
    burst_remain <= burst_remain - 1;

assign local_burstbegin = ((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_READ)); /*产生local burst begin信号*/

state=MEM_WRITE_BURST_BEGIN , next_state= IDLE

(local_ready && wr_remain_len == 10'd1) ==1    /*如果写的剩余数据长度为1, Burst写结束*/
/*计算最后一个burst数据写请求信号*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_WRITE_BURST_BEGIN || state == MEM_WRITE)
			if(wr_remain_len == 10'd2 && local_ready)
				last_wr_burst_data_req <= 1'b1;
			else
				last_wr_burst_data_req <= last_wr_burst_data_req;
		else
			last_wr_burst_data_req <= 1'b0;
	end


if(local_ready)
    wr_remain_len <= wr_remain_len - 10'd1;
else
    wr_remain_len <= wr_remain_len;

if( ((state == MEM_WRITE_BURST_BEGIN) || (state == MEM_WRITE)) && local_ready)      /*一次数据写入有效*/
    burst_remain <= burst_remain - 1;

assign local_burstbegin = ((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_READ)); /*产生local burst begin信号*/

state= MEM_WRITE , next_state = MEM_WRITE_BURST_BEGIN

(burst_remain == 1 && local_ready)==1 /*一次local burst写完成,重新回到burst begin */ 
/*计算最后一个burst数据写请求信号*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_WRITE_BURST_BEGIN || state == MEM_WRITE)
			if(wr_remain_len == 10'd2 && local_ready)
				last_wr_burst_data_req <= 1'b1;
			else
				last_wr_burst_data_req <= last_wr_burst_data_req;
		else
			last_wr_burst_data_req <= 1'b0;
	end


MEM_WRITE:
if(local_ready)
    wr_remain_len <= wr_remain_len - 10'd1;
else
    wr_remain_len <= wr_remain_len;

if(next_state == MEM_WRITE_BURST_BEGIN)
    burst_remain <= burst_size;        /*burst size is 2*/

if( ((state == MEM_WRITE_BURST_BEGIN) || (state == MEM_WRITE)) && local_ready)      /*一次数据写入有效*/
    burst_remain <= burst_remain - 1;

if(state == MEM_WRITE && (next_state == MEM_WRITE_BURST_BEGIN))
    if((wr_remain_len - 1) > burst_size)  /*判断剩余写数据长度是否大于burst_size*/
        local_size <= burst_size;
else
    local_size <= wr_remain_len - 1;


if(local_ready && (next_state == MEM_WRITE_BURST_BEGIN))    /*MEM_WRITE再写两个数据*/
    begin
        local_address <= local_address + {14'd0,burst_size};   /*Bust 写,地址加burst_size*/
    end
elses
    begin
        local_address <= local_address;
    end	                                                   /*上面两个状态走完则已经写了4个数据即32bit*/

assign wr_burst_finish = (local_ready && wr_remain_len == 10'd1);

state= MEM_WRITE , next_state = IDLE

(wr_remain_len == 10'd1 && local_ready) ==1   /*如果写的剩余数据长度为1, Burst写结束*/
/*计算最后一个burst数据写请求信号*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_WRITE_BURST_BEGIN || state == MEM_WRITE)
			if(wr_remain_len == 10'd2 && local_ready)
				last_wr_burst_data_req <= 1'b1;
			else
				last_wr_burst_data_req <= last_wr_burst_data_req;
		else
			last_wr_burst_data_req <= 1'b0;
	end


MEM_WRITE:
if(local_ready)
    wr_remain_len <= wr_remain_len - 10'd1;
else
    wr_remain_len <= wr_remain_len;

if( ((state == MEM_WRITE_BURST_BEGIN) || (state == MEM_WRITE)) && local_ready)      /*一次数据写入有效*/
    burst_remain <= burst_remain - 1;

assign wr_burst_finish = (local_ready && wr_remain_len == 10'd1);

state=IDLE , next_state=MEM_READ

if(state == IDLE && rd_burst_req)
    local_size <= (rd_burst_len >= burst_size) ?  burst_size : rd_burst_len ;
else if(state == IDLE && wr_burst_req)
    local_size <= (wr_burst_len >= burst_size) ?  burst_size : wr_burst_len;

/*burst读长度*/	
always@(posedge	mem_clk)
	begin
		if(state == IDLE && rd_burst_req)
			length <= rd_burst_len;
		else
			length <= length; 
	end

state= MEM_READ, next_state = MEM_READ

if(state == MEM_READ && local_ready )
    local_size <= (rd_addr_cnt + burst_size > length) ? 1 : burst_size; 
if(local_ready)
    begin
        local_address <= local_address + {14'd0,burst_size};   /*Bust读,地址加burst_size*/
        rd_addr_cnt <= rd_addr_cnt + burst_size;
    end
else
    begin
        local_address <= local_address;
        rd_addr_cnt <= rd_addr_cnt;
    end		

/*统计读数据counter*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_READ || state == MEM_READ_WAIT)
			if(local_rdata_valid)
				rd_data_cnt <= rd_data_cnt + 10'd1;
			else
				rd_data_cnt <= rd_data_cnt;
		else
			rd_data_cnt <= 10'd0;
	end

assign local_read_req = (state == MEM_READ);

assign local_burstbegin = ((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_READ)); /*产生local burst begin信号*/

state= MEM_READ, next_state = MEM_READ_WAIT

if(state == MEM_READ && local_ready )
    local_size <= (rd_addr_cnt + burst_size > length) ? 1 : burst_size; 

if(local_ready)
    begin
        local_address <= local_address + {14'd0,burst_size};   /*Bust读,地址加burst_size*/
        rd_addr_cnt <= rd_addr_cnt + burst_size;
    end
else
    begin
        local_address <= local_address;
        rd_addr_cnt <= rd_addr_cnt;
    end		

/*统计读数据counter*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_READ || state == MEM_READ_WAIT)
			if(local_rdata_valid)
				rd_data_cnt <= rd_data_cnt + 10'd1;
			else
				rd_data_cnt <= rd_data_cnt;
		else
			rd_data_cnt <= 10'd0;
	end

assign local_read_req = (state == MEM_READ);

assign local_burstbegin = ((state == MEM_WRITE_BURST_BEGIN) ||  (state == MEM_READ)); /*产生local burst begin信号*/

state= MEM_READ_WAIT, next_state = MEM_READ_WAIT

MEM_READ_WAIT:                   /*等待burst数据读完成*/
begin 
    if(rd_data_cnt == length - 10'd1 && local_rdata_valid)     /*判断读出的有效数据长度*/
        next_state <= IDLE;
    else
        next_state <= MEM_READ_WAIT;
end

/*统计读数据counter*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_READ || state == MEM_READ_WAIT)
			if(local_rdata_valid)
				rd_data_cnt <= rd_data_cnt + 10'd1;
			else
				rd_data_cnt <= rd_data_cnt;
		else
			rd_data_cnt <= 10'd0;
	end

state= MEM_READ_WAIT, next_state = IDLE

MEM_READ_WAIT:                   /*等待burst数据读完成*/
begin 
    if(rd_data_cnt == length - 10'd1 && local_rdata_valid)     /*判断读出的有效数据长度*/
        next_state <= IDLE;
    else
        next_state <= MEM_READ_WAIT;
end

/*统计读数据counter*/
always@(posedge	mem_clk)
	begin
		if(state == MEM_READ || state == MEM_READ_WAIT)
			if(local_rdata_valid)
				rd_data_cnt <= rd_data_cnt + 10'd1;
			else
				rd_data_cnt <= rd_data_cnt;
		else
			rd_data_cnt <= 10'd0;
	end

assign rd_burst_finish = (state == MEM_READ_WAIT) && (next_state == IDLE);

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